Datasheet4U Logo Datasheet4U.com

ZL30100 - T1/E1 System Synchronizer

General Description

The ZL30100 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for multi-trunk T1 and E1 transmission equipment.

The ZL30100 generates ST-BUS and other TDM clock and framing signals that are phase locked to one of two input references.

Key Features

  • April 2010.
  • Supports Telcordia GR-1244-CORE Stratum 4 and Stratum 4E.
  • Supports ITU-T G.823 and G.824 for 2048 kbit/s and 1544 kbit/s interfaces.
  • Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces Ordering Information ZL30100QDG1 64 Pin TQFP.
  • Trays, Bake & Drypack.
  • Pb Free Matte Tin -40°C to +85°C.
  • Simple hardware control interface.
  • Accepts two input references and synchronizes to any combination of 8 kHz, 1.544 MHz,.

📥 Download Datasheet

Datasheet Details

Part number ZL30100
Manufacturer Zarlink Semiconductor Inc
File Size 436.73 KB
Description T1/E1 System Synchronizer
Datasheet download datasheet ZL30100 Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
ZL30102 T1/E1 Stratum 4/4E Redundant System Clock Synchronizer Zarlink Semiconductor
ZL30105 T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer Zarlink Semiconductor
ZL30106 SONET/SDH/PDH Network Interface DPLL Zarlink
ZL30107 GbE Line Card Synchronizer Zarlink Semiconductor
ZL30108 SONET/SDH Network Interface DPLL Zarlink Semiconductor

Other Datasheets by Zarlink Semiconductor Inc

Part Number Description
ZL30101 T1/E1 Stratum 3 System Synchronizer
ZL30402 SONET/SDH Network Element PLL
ZL30407 SONET/SDH Network Element PLL
ZL30409 T1/E1 System Synchronizer with Stratum 3 Holdover
ZL38001 Low-Voltage Acoustic Echo Canceller with Low ERL Compensation

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
ZL30100 T1/E1 System Synchronizer Data Sheet Features April 2010 • Supports Telcordia GR-1244-CORE Stratum 4 and Stratum 4E • Supports ITU-T G.823 and G.824 for 2048 kbit/s and 1544 kbit/s interfaces • Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces Ordering Information ZL30100QDG1 64 Pin TQFP* Trays, Bake & Drypack *Pb Free Matte Tin -40°C to +85°C • Simple hardware control interface • Accepts two input references and synchronizes to any combination of 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz or 16.384 MHz inputs • Less than 0.6 nspp intrinsic jitter on all output clocks • External master clock source: clock oscillator or crystal • Provides a range of clock outputs: 1.544 MHz, 2.048 MHz, 16.384 MHz and either 4.096 MHz and 8.192 MHz or 32.768 MHz and 65.